1. Field of the Invention
The present invention relates to a method and an apparatus for estimating a sampling delay error of a time-interleaved analog-to-digital converter (ADC) for calibrating sampling delay between sub-ADCs.
2. Description of the Prior Art
Current demand for an operating frequency of a state of the art ADC is over 1 GHz. Due to implementation challenges of the analog circuits, a time-interleaved ADC has been developed. In the time-interleaved ADC, the same input signal is sampled by multiple sub-ADCs, each operating at a lower frequency, to generate digital output results. The digital output results are then combined in a time-interleaved manner to produce a sampling result which is equivalent to an output that should be generated from an ADC with a high sampling frequency.
Taking a two-path sub-ADC (which includes a first ADC and a second ADC) for example, the first ADC outputs odd-numbered sampling values (i.e. sampling values indexed by 1, 3, 5 . . . ) and the second ADC outputs even-numbered sampling values (i.e. sampling values indexed by 2, 4, 6 . . . ). The odd-numbered sampling values and the even-numbered sampling values are then merged into consecutive numbered sampling values (i.e. sampling values indexed by 1, 2, 3, 4, 5, 6 . . . ). Although the sampling intervals (i.e. sampling periods) of the first and the second ADCs are both 2*Ts, the sampling interval of the merged output is not guaranteed to be Ts uniformly due to an inherent sampling delay error between the sub-ADCs. In an ideal Case, the sampled values indexed by 1, 3, 5 . . . are sampled at respective time Ts, 3*Ts, 5*Ts . . . . The sampled values indexed by 2, 4, 6 . . . are sampled at respective time 2*Ts, 4*Ts, 6*Ts . . . . The ideal sampling delay (i.e. the delay time between the sampling time of the first ADC and the sampling time of the second ADC) between the first and the second ADCs is Ts, but the existence of the sampling delay error makes the real digital output of the time-interleaved ADC inconsistent with the expected output. It is assumed that a sampling delay error Te is incorporated into the sampling time of the odd-numbered sampled values output by the first ADC. In this case, sampled values indexed by 1, 3, 5 . . . are sampled at respective time Ts+Te, 3*Ts+Te, 5*Ts+Te . . . . In specific, this is equivalent to adding a sampling delay error −Te to the sampling time of the even-numbered sampled values output by the second ADC.
Therefore, there is a need for a novel method to estimate sampling delay error for calibrating the sampling time of the sub-ADCs in the time-interleaved ADC and compensating the sampling delay error Te.